View SGP08G72D1BD2SA-BBRT_8152498.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 8 g b ddr3 C registered ulp dimm 240 pin registered ulp dimm sgp0 8g72d1b d 2 sa - xx r t 8 gb in fbga technology rohs compliant environmental requirements: ? operating temperature (ambient) standard grade 0c to 70c w - grade - 40c to 85c ? operating humidity 10% to 90% relative humidity, non condensing ? operating pressure 105 to 69 kpa (up to 10000 ft.) ? storage temperature - 55c to 100c ? storage humidity 5% to 95% relative humidity, non condensing ? storage pressure 1682 psi (up to 5000 ft.) at 50c options: ? data rate / latency marking ddr3 1066 m t/s cl7 - bb ddr3 1333 m t/s cl9 - cc ? module density 8 gb with 18 dies and 2 ranks ? standard grade (t a ) 0c to 70c (t c ) 0c to 85c ? w - grade (t a ) - 40c to 85c (t c ) - 40c to 95c *) *) the refresh rate has to be doubled when 85c preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 this swissbit module is an industry standard 240 - pin 8 - byte ddr3 registered sdram dual - in - line memory module ( r dimm) which is organized as x 72 high speed cmos memory array . all control and address signals are re - driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. de - coupling capacitors, stub resistors, calibration resistors and termination resistors are mounted on the pcb board. the module uses double data rate architecture to achieve high - speed operation. ddr3 sdram modules operate from a differential clock (ck and ck#). read and write accesses to a ddr3 sdram module is burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. the burst length is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr3 sdram devices have a multibank architecture which allows a concurrent operation that is provid ing a high effective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_15 compatible. the ddr3 sdram module uses the serial presence detect (spd) function implemented vi a serial eeprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the dimm manufacturer (swissbit) to identify the module type, the modules organization and several timing parameters. the second 128 bytes are available to the end user. module configuration organization ddr3 sdrams used row addr. device bank addr. column addr. refresh module bank select 1g x 72 bit 1 8 x 512 m x 8bit ( 4 g bit) 1 6 ba0, ba1, ba2 10 8k s0#, s1# module dimen sions in mm 133.35 (long) x 17.75 (high) x 4 .00 [max] (thickness) timing parameters part number module density transfer rate clock cycle /data bit rate latency sgp0 8 g72d1b d 2 sa - bbr t 8 gb yte 8.5 gb/s 1.87ns / 1066mt/s 7 - 7 - 7 sgp08 g72d1b d 2 sa - ccr t 8 gb yte 10.6 g b/s 1.5ns / 1333mt/s 9 - 9 - 9 pin name a0 C a9, a11, a13 C a1 5 address inputs a10/ap address input / auto precharge bit a12/bc address input / burst chop ba0 C ba2 bank address inputs dq0 C dq63 data input / output cb0 C cb7 data check bits input / out put dqs0 C dqs8 data strobe, positive line dqs0# C dqs8# data strobe, negative line (only used when differential data strobe mode is enabled) tdqs9 - 17, tdqs9 - 17# terminate dqs, input for on die termination of x4 based dqs9 - 17 [#] signals s0#, s1# chip s elect ras# row address strobe cas# column address strobe we# write enable cke0 C cke1 clock enable figure 1: mechanical dimensions
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ck0 C ck1 clock inputs, positive line ck0# C ck1 # clock inputs, negative line event# temperature event: the event# pin is asserted by the temperature sensor when critical v dd supply voltage (1.5v 0.075v) v ref dq reference voltage: dq, dm (v dd /2) v ref ca reference voltage: control, command, and address (v dd /2) v ss ground v tt termination voltage: used for control, command, and address (v dd /2). v ddsp d serial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa2 serial presence detect address inputs odt0, odt1 on - die termination nc / nu no connection / not used pin configuration fron tside pin symbol pin symbol pin symbol pin symbol pin symbol 1 v ref dq 27 dq18 49 v tt 75 v dd 101 v ss 2 v ss 28 dq19 50 cke0 76 s1# 102 dqs6# 3 dq0 29 v ss 51 v dd 77 odt1 103 dqs6 4 dq1 30 dq24 52 ba2 78 v dd 104 v ss 5 v ss 31 dq25 53 err_out# 79 nc ( s2# ) * 105 dq50 6 dqs0# 32 v ss 54 v dd 80 v ss 106 dq51 7 dqs0 33 dqs3# 55 a11 81 dq32 107 v ss 8 v ss 34 dqs3 56 a7 82 dq33 108 dq56 9 dq2 35 v ss 57 v dd 83 v ss 109 dq57 10 dq3 36 dq26 58 a5 84 dqs4# 110 v ss 11 v ss 37 dq27 59 a4 85 dqs4 111 dqs7# 12 dq8 38 v ss 60 v dd 86 v ss 112 dqs7 13 dq9 39 cb0 61 a2 87 dq34 113 v ss 14 v ss 40 cb1 62 v dd 88 dq35 114 dq58 15 dqs1# 41 v ss 63 rfu 89 v ss 115 dq59 16 dqs1 42 dqs8# 64 rfu 90 dq40 116 v ss 17 v ss 43 dqs8 65 v dd 91 dq41 117 sa0 18 dq10 44 v ss 66 v dd 92 v ss 118 scl 19 dq11 45 cb2 67 v ref ca 93 dqs5# 119 sa2 20 v ss 46 cb3 68 par_in 94 dqs5 120 v tt 21 dq16 47 v ss 69 v dd 95 v ss 22 dq17 48 v tt 70 a10/ ap 96 dq42 23 v ss 71 ba0 97 dq43 24 dqs2# 72 v dd 98 v ss 25 dqs2 73 we# 99 dq48 26 v ss 74 cas # 100 dq49
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 backside pin symbol pin symbol pin symbol pin symbol pin symbol 121 v ss 147 dq23 169 cke1 195 odt0 221 t dqs 15 122 dq4 148 v ss 170 v dd 196 a13 222 t dqs 15# 123 dq5 149 dq28 171 a15 197 v dd 223 v ss 124 v ss 150 dq29 172 a14 198 nc ( s3# ) * 224 dq54 125 t dqs9 151 v ss 173 v dd 199 v ss 225 dq55 126 t dqs9# 152 t dqs12 174 a12, bc 200 dq36 226 v ss 127 v ss 153 t dqs12# 175 a9 201 dq37 227 dq60 128 dq6 154 v ss 176 v dd 202 v ss 228 dq61 129 dq7 155 dq30 177 a8 203 t dqs 13 229 v ss 130 v ss 156 dq31 178 a6 204 t dqs 13# 230 t dqs 16 131 dq12 157 v ss 179 v dd 205 v ss 231 t dqs 16# 132 dq13 158 cb4 180 a3 206 dq38 232 v ss 133 v ss 159 cb5 181 a1 207 dq39 233 dq62 134 t dqs 10 160 v ss 182 v dd 208 v ss 234 dq63 135 t dqs 10# 161 t dqs 17 183 v dd 209 dq44 235 v ss 136 v ss 162 t dqs 17# 184 ck0 210 dq45 236 v ddspd 137 dq14 163 v ss 185 ck0# 211 v ss 237 sa1 138 dq15 164 cb6 186 v dd 212 t dqs 14 238 sda 139 v ss 165 cb7 187 nc 213 t dqs 14# 239 event# 140 dq20 166 v ss 188 a0 214 v ss 240 v tt 141 dq21 167 nc(test) 189 v dd 2 15 dq46 142 v ss 168 reset# 190 ba1 216 dq47 143 t dqs 11 191 v dd 217 v ss 144 t dqs 11# 192 ras# 218 dq52 145 v ss 193 s0# 219 dq53 146 dq22 194 v dd 220 v ss *) following pin functions are depending on module configuration: ? s1# is conne cted, but not used functionally for single rank dimms ? odt1 , cke1 are not used for single rank modules ? s2# and s3# are only used for q uad rank modules ? event# is only used with temperature sensor equipped modules ? a13, a14, a15 are included in parity calculat ion. function depends on dram address configuration. a13 used for 1gb, a13 & a14 for 2gb, a13 - a15 for 4gb sdram
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 functional block diagramm 8192 mb ddr3 sdram r dimm, 2 ranks and 1 8 components dq 0 dq 1 dq 2 dq 3 dq 5 dq 4 dq 6 dq 7 rs 0 zq rs 1 vss dqs 0 dqs 0 dm 0 / tdqs 9 nc / tdqs 9 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 1 dqs cs nu / tdqs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 9 dqs cs nu / tdqs dq 32 dq 33 dq 34 dq 35 dq 37 dq 36 dq 38 dq 39 zq vss dqs 4 dqs 4 dm 4 / tdqs 13 nc / tdqs 13 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 5 dqs cs nu / tdqs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 13 dqs cs nu / tdqs dq 8 dq 9 dq 10 dq 11 dq 13 dq 12 dq 14 dq 15 zq vss dqs 1 dqs 1 dm 1 / tdqs 10 nc / tdqs 10 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 2 dqs cs nu / tdqs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 10 dqs cs nu / tdqs dq 16 dq 17 dq 18 dq 19 dq 21 dq 20 dq 22 dq 23 zq vss dqs 2 dqs 2 dm 2 / tdqs 11 nc / tdqs 11 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 3 dqs cs nu / tdqs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 11 dqs cs nu / tdqs dq 24 dq 25 dq 26 dq 27 dq 29 dq 28 dq 30 dq 31 zq vss dqs 3 dqs 3 dm 3 / tdqs 12 nc / tdqs 12 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 4 dqs cs nu / tdqs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 12 dqs cs nu / tdqs cb 0 cb 1 cb 2 cb 3 cb 5 cb 4 cb 6 cb 7 zq vss dqs 0 dqs 0 dm 0 / tdqs 9 nc / tdqs 9 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 17 dqs cs nu / tdqs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 18 dqs cs nu / tdqs dq 40 dq 41 dq 42 dq 43 dq 45 dq 44 dq 46 dq 47 zq vss dqs 5 dqs 5 dm 5 / tdqs 14 nc / tdqs 14 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 6 dqs cs nu / tdqs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 14 dqs cs nu / tdqs dq 48 dq 49 dq 50 dq 51 dq 53 dq 52 dq 54 dq 55 zq vss dqs 6 dqs 6 dm 6 / tdqs 15 nc / tdqs 15 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 7 dqs cs nu / tdqs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 15 dqs cs nu / tdqs dq 56 dq 57 dq 58 dq 59 dq 61 dq 60 dq 62 dq 63 zq vss dqs 7 dqs 7 dm 7 / tdqs 16 nc / dqs 16 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 8 dqs cs nu / tdqs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm / tdqs dqs u 16 dqs cs nu / tdqs zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq vss vss vss vss vss vss vss vss vss s 0 s 1 ba [ 0 : 2 ] a [ 0 : 15 ] ras cas we cke 0 cke 1 odt 0 odt 1 par _ in ck 0 ck 0 reset r e g i s t e r a n d p l l rs 0 rank 0 rs 1 rank 1 rba 0 - rba 2 : ddr 3 sdram ra [ 15 : 0 ]: ddr 3 sdram rras ddr 3 sdram rcas ddr 3 sdram rwe ddr 3 sdram rcke 0 : rank 0 rcke 1 : rank 1 rodt 0 : rank 0 rodt 1 : rank 1 err _ out ddr 3 sdram ck ck ddr 3 sdram u 19 v ddspd v dd v tt v refca v refdq v ss temperature sensor / spd eeprom ddr 3 sdram ddr 3 sdram ddr 3 sdram ddr 3 sdram ddr 3 sdram evt a 0 a 1 a 2 scl sda event sa 0 sa 1 sa 2 u 20 scl sda
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 maximum electrical dc characteristics parameter/ condition sym bol min max units v dd supply voltage relative to v ss v dd - 0.4 1.975 v i/o v dd supply voltage relative to v ss v dd q - 0.4 1.975 v voltage on any pin relative to v ss v in , v out - 0.4 1.975 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 16 16 ck, ck# - 16 16 dm - 2 2 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 8 8 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.425 1.5 1.575 v i/o supply voltage v dd q 1.425 1.5 1.575 v v dd l suppl y voltage v dd l 1.425 1.5 1.575 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt 0.49 x v dd q - 20mv 0.50 x v dd q 0.51x v dd q +20mv v input high (logic 1) voltage v ih (dc) v ref + 0.1 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.175 - v input low (logic 0) voltage v il (ac) - v ref - 0.175 v capacitance at ddr3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gr oss estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 i dd specifications and conditions (0c t case + 85c; v dd q = +1.5v 0. 075v, v dd = +1.5v 0.075v) parameter & test condition symbol max. unit 10600 - cl9 8500 - cl7 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands; dq inputs changin g once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 1030 982 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min ( i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 11 2 9 1081 ma precharge power - down current: all device banks idle; power - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast exit i dd2p 778 738 ma slow exit 778 738 precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 846 806 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd2n 884 844 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref (always fast exit) i dd3p 778 738 ma active standby current : all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd3n 1018 942 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands ; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 1354 1234 ma
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 parameter & test condition symbol max. unit 10600 - cl9 8500 - cl7 operating write current: all device banks open, continuous bu rst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing o nce per clock cycle i dd4w 1364 1244 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inp uts changing once per clock cycle i dd5 2539 2499 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dqs are floating at v ref i dd6 300 300 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t r c = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1948 1882 ma *) value calculated as one module rank in this op erating condition, and all other idle ranks in idd2 n mode. timing values used for i dd measurement i dd measurement conditions symbol 10600 - cl9 8500 - cl7 unit cl (i dd ) 9 7 t ck t rcd (i dd ) 13.5 13.125 ns t rc (i dd ) 49.5 50.625 ns t rrd (i dd ) 6 7.5 ns t ck (i dd ) 1.5 1 . 87 ns t ras min (i dd ) 36 37.5 ns t ras max (i dd ) 70 200 70 200 ns t rp (i dd ) 13.5 13.125 ns t rfc (i dd ) 2 60 2 60 ns
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electrical characteristics and recommended ac operating conditions (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 10600 - cl9 8500 - cl7 parameter symbol min max min max unit clock cycle time cl = 10 t ck (10) 1.5 <1.875 - - ns cl = 9 t ck (9) 1.5 <1.875 - - ns cl = 8 t ck (8) 1.875 <2.5 - - ns cl = 7 t ck (7) 1.875 <2.5 1.875 <2.5 ns cl = 6 t ck (6) 2.5 3.3 2.5 3.3 ns ck high - level width t ch (avg) 0.47 0.53 0.47 0.53 t ck ck low - level width t cl (avg) 0.47 0.53 0.47 0.53 t ck data - out high - impedance window from ck/ck# t hz - 250 - 300 ps data - out low - impedance window from ck/ck# t lz - 500 250 - 600 300 ps dq and dm input setup time relative to dqs t ds(base) 30 - 25 - ps dq and dm input hold time relative to dqs t dh(base) 65 - 100 - ps dq and dm input setup time relative to dqs v ref =1v/ns t ds1v 180 - 200 - ps dq and dm input hold time relative to dqs v ref =1v/ns t dh1v 165 - 200 - ps dq and dm input pulse width ( for each input ) t dipw 400 - 490 - ps dqs, dqs# to dq skew, per access t dqsq - 125 - 150 ps dq - dqs hold, dqs to first dq to go non - valid, per access t qh 0.38 - 0.38 - t ck (avg) dqs input high pulse width t dqsh 0.45 0.55 0.45 0.55 t ck dqs input low pulse width t dqsl 0.45 0.55 0.45 0.55 t ck dqs, dqs# rising to/from ck, ck# t dqsck - 255 255 - 300 300 ps dqs, dqs# rising to/from ck, ck# when dll disable d t dqsck dll_dis 1 10 1 10 ns dqs falling edge to ck rising - setup time t dss 0.2 - 0.2 - t ck dqs falling edge from ck rising - hold time t dsh 0.2 - 0.2 - t ck dqs read preamble t rpre 0.9 note 1 0.9 note 1 t ck dqs read postamble t rpst 0.3 note 2 0.3 note 2 t ck dqs write preamble t wpre 0.9 - 0.9 - t ck dqs write postamble t wpst 0.3 - 0.3 - t ck positive dqs latching edge to associated clock edge t dqss - 0.25 + 0.25 - 0.25 + 0.25 t ck address and control input pulse width ( for each input ) t ipw 620 - 780 - ps ctrl, cmd, addr setup to ck, ck# t is(base) 65 - 125 - ps ctrl, cmd, addr setup to ck, ck# v ref @ 1v/ns t is(1v) 240 - 300 - ps 1 the maximum preamble is bound by t lzdqs (max) 2 the maximum postamble is bound by t hzdqs (max)
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electric al characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 10600 - cl9 8500 - cl7 parameter symbol min max min max unit ctrl, cmd, addr hold to ck,c k# t ih (base) 140 - 200 - ps ctrl, cmd, addr hold to ck, ck# v ref @ 1v/ns t ih(1v) 240 - 300 - ps cas# to cas# command delay t ccd 4 - 4 - t ck act to act (same bank) command period t rc 49.5 - 50.625 - ns act bank a to act bank b command t rrd max 4nck,10ns - max 4nck,7.5ns - ns act to read or write delay t rcd 13.5 - 13.125 - ns four bank activate period 1k page size t faw 30 - 37.5 - ns 2k page size 45 - 50 - act to pre command t ras 36 70 t rtp max 4nck, 7.5ns - max 4nck,7.5ns - ns write recovery time t wr 15 - 15 - ns auto precharge write recovery + precharge time t dal t wr + t rp /t ck - t wr + t rp /t ck - ns internal write to read command delay t wtr max 4nck,7.5ns - max 4nck,7.5ns - ns pre command period t rp 13.5 - 13.125 - ns load mode command cycle time t mrd 4 - 4 - t ck ref to act or ref to ref command interval t rfc 260 70 (0c<= t case <= 85 c) t refi - 7.8 - 7.8 s (85c<= t case <= 95 c ) t refi (it) - 3.9 - 3. 9 s rtt turn - on from odtl on reference t aon - 250 250 - 300 300 ps rtt turn - on from odtl off reference t aof 0.3 0.7 0.3 0.7 t ck asynchronous rtt turn - on delay (power down with dll off) t aonpd 2 8,5 2 8,5 ns asynchronous rtt turn - off delay (power down with dll off) t aofpd 2 8,5 2 8,5 ns rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 t ck exit self refresh to commands not requiring a locked dll t xs max 5nck,tr fc + 10ns - max 5nck,tr fc + 10ns - ns write levelling setup fro m rising ck, ck# crossing to rising dqs, dqs# crossing t wls 195 - 245 - ps write levelling setup from rising dqs, dqs# crossing to rising ck, ck# crossing t wlh 195 - 245 - ps first dqs, dqs# rising edge t wlmrd 40 - 40 - t ck dqs, dqs# delay t wldqsen 25 - 25 - t ck exit reset from cke high to a valid command t xpr max 5nck, trfc + 10ns - max 5nck, trfc + 10ns - t ck begin power supply ramp to power supplies stable t vddpr - 200 - 200 ms
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 10600 - cl9 8500 - cl7 parameter symbol min max min max unit reset# low to power supplies stable t rps - 200 - 200 ms reset# low to i/ o and rtt high - z t ioz - 20 - 20 ns exit precharge power - down to any non - read command t xp max 3nck,6ns - max 3nck,7.5ns - t ck cke minimum high/low time t cke max 3nck, 5.625ns - max 3nck, 5.625ns - t ck register specifications parameter symbol pins min m ax units dv supply voltage v dd - 1.425 1.575 v dc reference voltage v ref - 0.49 v dd - 20mv 0.51 v dd + 20mv v dc termination voltage v tt - 0.49 v dd - 20mv 0.51 v dd + 20mv v dc high - level input voltage v ih ( dc ) address, control, command v ref + 100 v dd + 400 mv dc low - level input voltage v il(dc) address, control, command - 400 v ref C 100 mv ac high - level input voltage v ih(ac) address, control, command v ref + 175 v dd + 400 mv ac low - level input voltage v il(ac) address, control, command - 400 v ref - 175 mv high - level output current i oh err_out# - t . b . d ma low - level output current i ol err_out# t . b . d t . b . d ma high - level input voltage v ih (cmos) reset#, mirror 0.65 v dd v dd v low - level input voltage v il (cmos) reset#, mirror 0 .35 v dd v different ial input cross point voltage range v ix (ac) ck, ck#, fbin, fbin# 0.5 v d d - 175mv 0.5 v d d + 175mv v differential input voltage v id (ac) ck, ck# 350 t . b . d mv notes: 1. timing and switching specifications for the register listed above are critical for p roper operation of the ddr3 sdram rdimms. these are meant to be a subset of the parameters for the specific device used on the module. temperature sensor with serial presence - detect eeprom temperature sensor with serial pres ence - detect eeprom operating conditions parameter / condition symbol min max unit supply voltage v ddspd +3 +3.6 v supply current: v dd = 3.3v i dd +2.0 ma input high voltage: logic 1; scl, sda v ih +1.45 v ddspd +1 v input low voltage: logic 0; scl, sda v il - 550 mv output low voltage: i out = 2.1ma v ol - 400 mv input current i in - 5.0 5.0 a temperature sensing range t . b . d t . b . d c temperature sensor accuracy t . b . d t . b . d c s c l s d a e v e n t s a 2 s a 2 s a 1 s a 1 s a 0 s a 0 e v e n t w p / r 1 0
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 a.c. characteristics of temperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c symbol parameter / condition m i n max unit f scl scl clock frequency 10 400 khz t buf bus free time between stop and start 1300 ns t f sda fall time 300 ns t r sda rise time 300 ns t hd:dat data hold time (accepted for input data) 0 n s data hold time (guaranteed for output data) 300 900 ns t h:sta start condition hold time 600 ns t high high period of scl 600 ns t low low period of scl 1300 ns t su:dat data setup time 100 ns t su:sta start condition setup time 600 ns t su:sto st op condition setup time 600 ns t timeout smbus scl clock low timeout 25 35 ms t i noise pulse filtered at scl and sda inputs 100 ns t wr write cycle time 5 ms t pu power - up delay to valid temperature recording 100 ms temperature characteristics of te mperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c parameter test conditions/comments max unit temperature reading error class b, jc42.4 compliant +75c t a +95c, active range +40c t a +125c, monitor range 40c t a 1 ja junction - to - ambient (still air) 92 c/w 1 power dissipation is defined as p j = (t j ? t a )/ ja , where tj is the junct ion temperature and ta is the ambient temperature. the thermal resistance value refers to the case of a package being used on a standard 2 - layer pcb. slave address bits of temperature sensor device device type identifier select address signals r/w# b7 1 b6 b5 b4 b3 b2 b1 b0 eeprom 1 0 1 0 a 2 a 1 a 0 r/w# temp. sensor 0 0 1 1 a 2 a 1 a 0 r/w# 1 the most significant bit, b7, is sent first.
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 byte byte description 10600 - cl9 8500 - cl7 0 crc range, eeprom bytes, bytes used 0x92 1 spd revison 0x1 2 2 dram devic e type 0x0b 3 module type (form factor) 0x0 1 4 sdram device density & banks 0x0 4 5 sdram device row & column count 0x 21 6 byte 6 reserved 0x00 7 module ranks & device dq count 0x09 8 ecc tag & module memory bus width 0x0b 9 fine timebase dividend/di visor 0x 11 10 medium timebase dividend 0x01 11 medium timebase divisor 0x08 12 min sdram cycle time ( t ck min ) 0x0c 0x0f 13 byte 13 reserved 0x00 14 cas latencies supported (cl4 => cl11) 0x3 e 0x1 e 15 cas latencies supported (cl12 => cl18) 0x00 16 min cas latency time ( t aa min ) 0x69 17 min write recovery time ( t wr min ) 0x78 18 min ras# to cas# delay ( t rcd min ) 0x69 19 min row active to row active delay ( t rrd min ) 0x30 0x3c 20 min row precharge delay ( t rp min ) 0x69 21 upper nibble for t ras & t rc 0x 11 22 min active to precharge delay ( t ras min ) 0x20 0x2c 23 min active to active/refresh delay ( t rc min ) 0x89 0x95 24 min refresh recovery delay ( t rfc min ) lsb 0x 2 0 25 min refresh recovery delay (t rfc min ) msb 0x0 8 26 min internal write to read cmd de lay ( t wtr min ) 0x3c 27 min internal read to precharge cmd delay ( t rtp min ) 0x3c 28 min four active window delay ( t faw min ) msb 0x00 0x01 29 min four active window delay ( t faw min ) lsb 0xf0 0x2c 30 sdram device output drivers supported 0x83 31 sdram de vice thermal & refresh options 0x01
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 byte byte description 10600 - cl9 8500 - cl7 32 ddr3 - module thermal sensor 0x80 33 - 59 bytes 33 - 59 reserved 0x00 60 module height (nominal) 0x0 3 61 module thickness (max) 0x11 62 reference raw card id 0x0 a 63 addres s mapping edge conector to dram 0x0 5 64 rdimm thermal heat spreader solution 0x00 65 register mfr id (lsb) 0x04 66 register mfr id (msb) 0xb3 67 register revision number 0x03 68 register type 0x00 69 rc1 (ms nibble) / rc0 (ls nibble) - reserved 0x00 70 rc3 (ms nibble) / rc2 (ls nibble) C drive strength, command/address 0x50 71 - 116 bytes 71 - 116 reseved 0x00 117 module mfr id (lsb) 0x83 118 module mfr id (msb) 0xda 119 module mfr location id x 120 module mfr year x 121 module mfr week x 122 - 125 module serial number x 126 - 127 crc 0x688e 0 xf319 128 - 145 module part number "sgp0 8 g72d1b d 2 sa - xx" 146 module die rev x 147 module pcb rev x 148 dram device mfr id (lsb) 0x80 149 dram device mfr (msb) 0xce 150 - 175 mfr reserved bytes 150 - 175 0x00 176 - 25 5 customer reserved bytes 176 - 255 0x ff part number code s g p 0 8 g 72 d1 b d 2 sa - cc * r ** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 *rohs compl. swissbit ag ddr3 - 1333 mt/s sdram d dr 3 2 4 0 pin registered dimm with parity support chip vendor ( samsung ) capacity ( 8 gb yte ) 2 module ranks width chip rev. d pcb - type ( s3a1e1 ) chip organisation x8 * optional / additional information ** t = thermal s ensor
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 15 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 revision history revision changes date 0.9 preliminary version 1 5 . 01 .201 4
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 16 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 locations swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 1117 e plaza drive unit e suites 105/205 eagle, id 83616 usa phone: +1 208 258 - 6254 fax: +1 208 938 - 4 525 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512 ________________________________
preliminary data sheet rev.0.9 1 5 . 01.2014 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 17 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 declaration of conformity we manufacturer: swissbit ag industriestrasse 4 ch - 9552 bronschhofen switzerland declare under our sole responsibility that the product product type: 8 gb ddr3 r dimm brand name: swissmemory? product series: ddr3 r dimm part number: s g p 08g72 d1 bd2sa - xxxrt to which this declaration relates is in conformity with the following directives: 2002/96/ec category 3 (weee) following the provisions of directive restriction of the use of certain hazardous substances 2011/65/eu swissbit ag, january 201 4 manuela k?gel head of quality management

▲Up To Search▲

Price & Availability of SGP08G72D1BD2SA-BBRT

	To Download SGP08G72D1BD2SA-BBRT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .